Intel’s Diamond Rapids Shifts Strategy: 192 Cores and the End of Hyper-Threading
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A Pivot in Parallelism
At Computex in Taipei, Intel unveiled the architectural blueprint for its next-generation server powerhouse: Diamond Rapids. The announcement marks a significant shift in how the company approaches high-performance computing (HPC), pushing raw core counts higher while fundamentally altering how those cores handle workloads.
The headline figure is a jump to 192 cores, representing a 50 percent increase over the previous generation. However, this growth comes with a surprising casualty. Intel has officially scrapped Hyper-Threading—the company’s branding for simultaneous multithreading (SMT)—for this lineup. First introduced in 2002, SMT allowed two threads to share a single execution core to maximize utilization. By removing it, Intel is effectively trading virtual threads for raw physical silicon, a move that reflects a broader trend of abandoning SMT in consumer chips to favor efficiency and predictability.
Interestingly, this move may not be permanent. Industry signals suggest Intel is already iterating on this decision for the subsequent generation, codenamed Coral Rapids, which is expected to bring SMT back into the fold. This suggests Diamond Rapids may serve as a massive architectural experiment in pure-core density.
The Chiplet War and 18A Fabrication
Under the hood, Diamond Rapids reveals that Intel is moving closer to the modular design philosophy that has allowed AMD to dominate the server market since the launch of Rome in 2019. The chip will be fabricated using the 18A-P process—a refined version of Intel’s 2nm-class technology—but the real story is the packaging.
Utilizing Foveros packaging tech, Diamond Rapids appears to use a disaggregated design. Renders from Intel’s press deck suggest a layout featuring two I/O dies serving four vertically stacked compute assemblies. Each of these four compute chiplets is expected to house 48 cores. By shifting the L3 cache to the base die, Intel frees up critical real estate on the compute tiles, a strategy mirrored in the recently launched Clearwater Forest processors.
This approach allows Intel to scale more effectively, though they still trail AMD’s aggressive roadmap. While 192 cores is a leap for Intel, AMD’s Venice Epyc is targeting 256 cores and may reach the market as early as a year before Diamond Rapids, which is slated for a 2027 release.
Memory Bandwidth and the IaaS Market
Diamond Rapids is not intended for general-purpose virtualization or basic storage servers. Instead, Intel is positioning it for high-demand Infrastructure-as-a-Service (IaaS) and high-performance-per-thread workloads. To support these appetite-heavy tasks, the chip features 16 channels of DDR5 memory.
While official clock speeds remain undisclosed, data from Clearwater Forest (8000 MT/s) and Granite Rapids (8800 MT/s) suggest that Diamond Rapids could push toward 9600 MT/s. This would potentially deliver 1.2 TB/s of bandwidth per socket, putting Intel on a direct collision course with Nvidia’s LPDDR5X-equipped Vera CPUs.
The Licensing Dilemma
The removal of SMT creates a complex situation for enterprise software licensing. Many hypervisor models, including those from VMware and RedHat, have historically revolved around thread counts or core-pairs. With Diamond Rapids, customers are essentially getting fewer threads per dollar compared to SMT-enabled predecessors.
To mitigate this, the industry may see a shift toward renting instances in core-pairs, similar to how Oracle manages its Ampere-based ARM instances. However, this will require significant coordination between Intel and the major software vendors to ensure the transition doesn’t alienate enterprise buyers.
Further technical specifics, including power draw and instructions per clock (IPC) gains, are expected to be detailed during Intel’s presentation at the Hot Chips symposium in August.
