Intel’s Diamond Rapids Hits 192 Cores, But at the Cost of Hyper-Threading
Table of Contents
A Core Count Surge with a Technical Trade-off
At Computex in Taipei, Intel provided a glimpse into the next evolution of its server silicon: Diamond Rapids. The upcoming Xeon lineup is designed to aggressively scale performance, pushing core counts to 192—a 50 percent leap over the previous generation. However, this increase in raw hardware comes with a surprising architectural pivot: the removal of Hyper-Threading.
Intel’s implementation of simultaneous multithreading (SMT), branded as Hyper-Threading since 2002, allowed two threads to share a single execution core to minimize idle cycles. While the technology rarely doubled actual throughput, it provided significant efficiency gains for heavily threaded workloads. After phasing the tech out of its consumer-facing processors, Intel is now removing it from the enterprise heart of its business.
The loss of SMT means that while Diamond Rapids has more physical cores, its total thread count is actually dropping by a quarter compared to predecessors. This creates a peculiar situation for the data center: Intel is trading virtual efficiency for raw physical density.
The 18A Architecture and the ‘Chiplet’ Shift
The hardware will be fabricated using Intel’s 18A-P process, a refined iteration of its 2nm-class node. More interesting, however, is the physical construction. Intel is moving further toward a disaggregated design that mirrors the success of AMD’s chiplet strategy.
Based on renders from Intel’s press deck, Diamond Rapids utilizes Foveros packaging to stack four vertically assembled compute assemblies atop two I/O dies. This layout is strikingly similar to the Fujitsu Monaka and Intel’s own Clearwater Forest, though Diamond Rapids appears more complex in its I/O distribution. By moving the L3 cache to the base die, Intel has freed up significant real estate on the compute chiplets, allowing for four 48-core clusters.
Whether the memory controllers reside on the base dies or the I/O dies remains a point of speculation. If Intel follows the AMD ‘Rome’ blueprint and houses them in the I/O die, it could drastically reduce the number of NUMA (Non-Uniform Memory Access) nodes, which is critical for reducing latency in high-performance computing (HPC) environments.
Market Positioning and the AMD Pressure
Intel isn’t just fighting its own architectural legacy; it’s fighting a clock. While 192 cores is a substantial jump, AMD is reportedly pushing even further with its 256-core Venice Epyc processors. More concerning for Intel is the timeline: Diamond Rapids is currently slated for 2027, potentially leaving a window where AMD holds a significant lead in core density.
The removal of Hyper-Threading also introduces a headache for software licensing. Many hypervisor models, such as those from VMware or RedHat, are priced based on sockets or cores but scaled by thread availability. Customers moving to Diamond Rapids may find themselves getting fewer virtual threads for their dollar, unless cloud providers like Oracle adopt ‘core-pair’ renting models similar to those used for Ampere-based ARM instances.
HPC Focus and Massive Bandwidth
Intel has been clear that Diamond Rapids isn’t intended for general-purpose virtualization or storage servers. Instead, it is “optimized for high-demand IaaS,” placing it in the same high-performance computing (HPC) bracket as the 6900P-series. To support these workloads, Intel is equipping the chip with a massive 16-channel DDR5 memory bus.
While official speeds haven’t been released, the trajectory suggests a leap. With Clearwater Forest hitting 8000 MT/s and Granite Rapids targeting 8800 MT/s on MRDIMMS, it is reasonable to expect Diamond Rapids to push toward 9600 MT/s. This would result in approximately 1.2 TB/s of bandwidth per socket—putting Intel on a direct collision course with the LPDDR5X-equipped Vera CPUs from Nvidia.
The industry now looks toward the Hot Chips conference in August, where Intel is expected to provide a more granular technical breakdown of power consumption and instructions per clock (IPC) gains.
