The Vertical Shift: Imec’s 2038 Roadmap Signals the End of Classical Transistor Scaling
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A Pivot Toward the Third Dimension
For decades, the semiconductor industry has operated on a simple, brutal premise: make things smaller to make them faster. But according to the latest process technology roadmap from Imec, the world’s leading research hub for nanoelectronics, that era of linear shrinking is nearing a physical and economic dead end.
The roadmap, developed in collaboration with industry titans like TSMC, Intel, Samsung, and ASML, outlines a trajectory that extends to 2038. While the industry continues to chase smaller numbers—targeting 3 angstrom-class (0.3nm) nodes by the late 2030s—the underlying data reveals a sobering reality. The Contact Poly Pitch (CPP), a critical metric for how tightly transistors are packed, is projected to stall at 42nm around the A10 node in 2030.
Essentially, we are reaching the limit of how close we can place transistors side-by-side on a flat plane. To keep the spirit of Moore’s Law alive, the industry is preparing to stop scaling out and start scaling up.
The Rise of CFETs and the Angstrom Era
We are currently entering the 2nm-class era, characterized by the shift to nanosheet transistors. However, Imec suggests that nanosheets will only carry the industry so far. By the A7 generation, expected around 2033, the roadmap introduces Complementary FETs (CFETs) as a viable production candidate.
Unlike current architectures where n-type and p-type transistors sit side-by-side, CFETs stack these components vertically. This architectural leap allows chipmakers to reclaim massive amounts of silicon real estate without needing to shrink the CPP further. According to Julien Ryckaert, VP of R&D at Imec, the transition to CFETs is a response to the mounting challenges of scaling conventional nanosheets.
The shift to verticality isn’t just about the transistors; it’s about how they are powered. Imec indicates that Backside Power Delivery Networks (BSPDN)—which move power routing to the bottom of the wafer to reduce congestion—will likely become mandatory for CFET implementations.
The Lithography Hurdle: Beyond High-NA
As the targets move toward A5 (2035) and eventually A3 (2038), the tools required to carve these features become increasingly exotic. While Intel is already pushing for the insertion of High-NA EUV (Extreme Ultraviolet) lithography at the A14 node, Imec’s projections suggest that even High-NA may not be enough for the final push.
To achieve the projected 39nm CPP and 50nm cell height of the A3 node by 2038, the industry may need to transition to Hyper-NA EUV scanners. This represents a massive capital expenditure risk, as each generation of EUV equipment costs hundreds of millions of dollars and requires an entire ecosystem of new photoresists and mask technologies.
Redefining Moore’s Law
The Imec roadmap effectively redefines the industry’s North Star. For fifty years, Moore’s Law was about shrinking the size of a single transistor. Now, density gains will come from structural complexity: stacking transistors, integrating memory vertically, and optimizing the 3D volume of the chip.
By the time the industry reaches 0.3nm in 2038, the “nanometer” label will be more of a marketing shorthand for density than a physical measurement of a gate. The focus has shifted from the art of the shrink to the art of the stack.
